module EX_MEM (
    input wire clk,
    input wire rst_n,
    input wire pause,
    input wire flush,

    input wire rf_we_i,
    input wire [1:0] wd_sel_i,
    input wire wen_i,
    input wire [1:0] sd_sel_i,
    input wire [2:0] ld_sel_i,
    input wire [31:0] pc4_i,
    input wire [31:0] ext_i,
    input wire [31:0] alu_c_i,
    input wire [31:0] rD2_i,
    input wire [4:0] wR_i,

    output reg rf_we_o,
    output reg [1:0] wd_sel_o,
    output reg wen_o,
    output reg [1:0] sd_sel_o,
    output reg [2:0] ld_sel_o,
    output reg [31:0] pc4_o,
    output reg [31:0] ext_o,
    output reg [31:0] alu_c_o,
    output reg [31:0] rD2_o,
    output reg [4:0] wR_o,

    input      [31:0] debug_pc_i,
    output reg [31:0] debug_pc_o,
    input             debug_have_inst_i,
    output reg        debug_have_inst_o
);

always @ (posedge clk or negedge rst_n) begin
    if(!rst_n)  debug_pc_o <= 32'b0;
    else        debug_pc_o <= debug_pc_i;
end

always @ (posedge clk or negedge rst_n) begin
    if(!rst_n)  debug_have_inst_o <= 1'b0;
    else        debug_have_inst_o <= debug_have_inst_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      rf_we_o <= 1'b0;
    else if(flush)  rf_we_o <= 1'b0;
    else if(pause)  rf_we_o <= rf_we_o;
    else            rf_we_o <= rf_we_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      wd_sel_o <= 2'b0;
    else if(flush)  wd_sel_o <= 2'b0;
    else if(pause)  wd_sel_o <= wd_sel_o;
    else            wd_sel_o <= wd_sel_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      wen_o <= 1'b0;
    else if(flush)  wen_o <= 1'b0;
    else if(pause)  wen_o <= wen_o;
    else            wen_o <= wen_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      sd_sel_o <= 2'b0;
    else if(flush)  sd_sel_o <= 2'b0;
    else if(pause)  sd_sel_o <= sd_sel_o;
    else            sd_sel_o <= sd_sel_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      ld_sel_o <= 3'b0;
    else if(flush)  ld_sel_o <= 3'b0;
    else if(pause)  ld_sel_o <= ld_sel_o;
    else            ld_sel_o <= ld_sel_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      pc4_o <= 32'b0;
    else if(flush)  pc4_o <= 32'b0;
    else if(pause)  pc4_o <= pc4_o;
    else            pc4_o <= pc4_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      ext_o <= 32'b0;
    else if(flush)  ext_o <= 32'b0;
    else if(pause)  ext_o <= ext_o;
    else            ext_o <= ext_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      alu_c_o <= 32'b0;
    else if(flush)  alu_c_o <= 32'b0;
    else if(pause)  alu_c_o <= alu_c_o;
    else            alu_c_o <= alu_c_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      rD2_o <= 32'b0;
    else if(flush)  rD2_o <= 32'b0;
    else if(pause)  rD2_o <= rD2_o;
    else            rD2_o <= rD2_i;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)      wR_o <= 5'b0;
    else if(flush)  wR_o <= 5'b0;
    else if(pause)  wR_o <= wR_o;
    else            wR_o <= wR_i;
end

endmodule